01 - 08 - 2026

Chipmakers’ Quest Beyond Silicon

Imagine attempting to build a house using bricks that crumble the moment you lay them down.

For decades, chip designers have faced a remarkably similar dilemma at the atomic level. As engineers shrank silicon transistors down to mere nanometers, the material began to fail: electrons started tunneling through physical barriers, heat spiked uncontrollably, and power leaked like water from a rusted pipe. Silicon had finally hit its absolute physical wall. To keep computing power growing, scientists realized they couldn’t just build smaller bricks—they had to invent an entirely new material.

That search for silicon’s successor has led researchers to two-dimensional materials, and scientists at the Moscow Institute of Physics and Technology (MIPT) have proposed Russia’s first industrially viable process for manufacturing transistors using molybdenum disulfide (MoS₂).

The breakthrough offers a way around silicon’s physical barriers, delivering transistors that are at least three times smaller and hundreds of times more energy-efficient than existing analogues, all while remaining compatible with classical computing systems.

Overcoming the Silicon Wall

Silicon remains the backbone of global microelectronics, but its era of continuous miniaturization is ending. As transistor gate lengths shrink into the sub-nanometer territory, quantum mechanics intervenes.

Current leakage spikes and thermal dissipation limits maximum processing performance. To bypass this limit, research teams globally are turning to transition metal dichalcogenides—two-dimensional semiconductors only a few atoms thick.

According to Ilya Zavidovsky, Senior Researcher at MIPT’s Center for Photonics and Two-Dimensional Materials, who was quoted in news outlet iz.ru, stated that molybdenum disulfide overcomes silicon’s physical channel thickness limit, dropping the baseline from roughly 2 nanometers down to 0.65 nanometers. This reduction slashes device power consumption and drastically lowers operational heat generation.

Solving the Contact Problem

While 2D materials have long promised a revolution in microelectronics, transitioning from laboratory benchmarks to commercial fabrication has proved difficult. The primary barrier involves attaching metallic electrical contacts to a monolayer sheet without destroying its delicate atomic lattice. Standard vacuum deposition causes high-energy metal atoms to strip away sulfur atoms, creating structural defects and degrading electrical conductivity.

MIPT researchers solved this contact bottleneck by using Atomic Layer Deposition to place an ultra-thin insulating buffer layer of titanium dioxide —just a few atoms thick—between the semiconductor and the metal electrode. As Roman Romanov, Senior Researcher at MIPT’s Atomic Layer Deposition Laboratory, highlights, inserting this atomic buffer protects the fragile 2D sheet, enabling reliable electrostatic control and preventing current leakage without damaging the material.

Industrial Compatibility and Future Applications

As the Atomic Layer Deposition is already a standard process in modern semiconductor fabrication facilities, this buffer-layer technique can be integrated into existing production lines without requiring a total overhaul of manufacturing infrastructure. Furthermore, the methodology extends beyond molybdenum disulfide to an entire family of 2D materials, including tungsten disulfide, molybdenum selenide, and tungsten selenide.

Evgeniy Vishnevsky, an expert on new materials at the Russian National Technology Initiative, points out three major commercial avenues for this technology. First, it enables next-generation high-density chips that pack significantly more computing power into vastly smaller physical footprints. Second, it paves the way for flexible and transparent electronics, such as flexible displays, smart textiles, and wearable sensors integrated directly into clothing or medical devices. Third, it provides drastic energy savings critical for battery-constrained IoT devices, mobile hardware, and massive data centers.

Commercial viability will ultimately depend on scaling and economic feasibility. Nikolai Shelepin of the Institute of Nanotechnologies and Microelectronics at the Russian Academy of Sciences notes that adopting this technology in commercial foundries will only happen if the operational performance gains clearly outweigh the capital expenditure of re-tooling existing fabrication plants.

Strategic Relevance for India’s Semicon 2.0 Vision

Developments in alternative semiconductor materials like molybdenum disulfide carry significant strategic implications for nations carving out their place in the global chip ecosystem, particularly India. Having established its initial semiconductor footprint with legacy node fabs, assembly, and testing facilities under India Semiconductor Mission 1.0, New Delhi is actively pivoting toward its ambitious Semicon 2.0 vision.

The core objective of India’s Semicon 2.0 policy is to move up the value chain from basic assembly and legacy nodes into cutting-edge R&D, compound semiconductors, advanced packaging, and next-generation materials like 2D transition metal dichalcogenides. Rather than solely chasing capital-intensive silicon miniaturization dominated by global incumbents, India’s broader strategy emphasizes leapfrogging into emerging frontier tech—such as flexible electronics, smart sensors, and ultra-low-power edge AI devices. Innovations in monolayer materials like molybdenum disulfide align directly with India’s push to build indigenous IP, foster domestic fabless design startups, and secure supply chain sovereignty in energy-efficient hardware.

Global Breakthroughs

This research aligns with a global push across major semiconductor hubs to replace silicon channels with 2D transition metal dichalcogenides.

In Asia, experimental pilot production lines for molybdenum-disulfide-based processors have been launched to explore lithography alternatives and bypass sub-nanometer manufacturing bottlenecks. At the same time, leading global foundries like TSMC and Europe’s IMEC research center have actively published research on low-damage contact deposition techniques using bismuth and titanium buffer layers to integrate monolayer materials into future sub-1nm Gate-All-Around transistor architectures.

Academic labs at institutions like Stanford and MIT have similarly focused on atomic-layer buffer interfaces to resolve contact resistance and structural damage when joining metals to 2D sheets.

Venkatesh G